Interconnection and packaging related issues are among the main factors that determine not only the number of circuits that can be integrated on an electronic computer chip ("chip"), but also the performance of the chip. These issues have gained in importance as advances in integrated circuit chip design have led to reduced feature sizes of transistors and enlarged chip dimensions. Industry has come to realize that merely having a fast chip will not result in a fast system; it must also be supported by an equally fast and reliable package.
Essentially, a package, or packaging, supplies the chip with signals and power, and performs other functions such as heat removal, physical support and protection from the environment. Another important function is simply to redistribute the tightly packed I/Os off the chip to the I/Os of a printed wiring board.
An example of a package-chip system is the "flip-chip" integrated circuit mounted on an area array organic package. Flip-chip mounting entails placing solder bumps on a die or chip, flipping the chip over, aligning the chip with the contact pads on a substrate, and re-flowing the solder balls in a furnace to establish bonding between the chip and the substrate. This method is advantageous in certain applications because the contact pads are distributed over the entire chip surface rather than being confined to the periphery as in wire bonding and most tape-automated bonding (TAB) techniques. As a result, the maximum number of I/O and power/ground terminals available can be increased, and signal and power/ground interconnections can be more efficiently routed on the chips.
With flip-chip packaging, thermal expansions due to material property mismatches between a semiconductor chip and a substrate of an organic chip package can cause strains at the solder bumps, and thus, could lead to failure of the chip/package connection. Regardless of which packaging technique is employed, material issues, such as the aforementioned thermally induced strain, cause a chip package designer to select and match chip packaging materials with great care.
The current trend in integrated circuit chip packaging technology is shifting from thick ceramic substrate-based interconnection circuit devices to relatively thinner organic substrate-based interconnection circuit devices for single chip modules (SCMs) and multi-chip modules (MCMs). However, when these relatively thinner organic substrate-based interconnection circuit devices are attached to a semiconductor chip or die using conventional bonding and assembly techniques and methods, the thinner structures of these interconnection circuit devices flex and bend more readily than the thicker ceramic substrate-based interconnection circuit devices. This occurs primarily because of the differences in the coefficients of thermal expansion (CTE) between the materials used in the organic substrate devices and the integrated circuit die or chip, and because of the mechanical stresses that occur when these interconnection devices and chips are bonded and assembled with conventional bonding and assembly techniques and methods.
A need exists for an improved method for assembling an integrated circuit chip package and an improved method for bonding a semiconductor chip on a substrate of an organic substrate-based interconnection circuit device which minimize mechanical stresses between the chip and the chip package or interconnection circuit device.